(1) Field of the Invention
The invention relates to a method for testing integrated circuit devices, and, more particularly, to a method to test multiple designs using a single, probe card design.
(2) Description of the Prior Art
Testing is a key enabling technology in the art of integrated circuit manufacturing. Typically, testing is performed at the wafer-level and at the packaging level. When a device is tested at the wafer level, coupling between the device under test (DUT) and the automated test system is made possible using a probe card. Referring now to FIG. 1, a simplified, automated test system is shown. Automated test equipment (ATE) 10 comprises a very high speed and high precision testing circuit. The ATE 10 is coupled to a wafer prober station 14. The wafer prober 14 contains a test head, or probe head 18. Wafers are loaded into the test head where they are placed on a wafer stage for testing.
The automated test system is typically a very expensive tool. It is therefore designed as a general-purpose tool to test a number of different integrated circuit designs. Flexibility of use is derived by storing a number of testing programs in the ATE 10 that may be selected by the user interface 22 prior to each test. In addition, it is well-known that integrated circuit devices employ a variety of input/output (I/O), power, and ground pin outs. Therefore, the test system must be able to account for these differences. Commonly, this flexibility is derived by using probe cards.
A probe card is an interface card between the probe head 18 and the DUT. The probe card translates the fixed pin-out capabilities, such as hard wired input channels or output channels, of the ATE into a flexible arrangement of pins custom interfaced to a specific IC design. In this way, the ATE system 10 can be used to test a number of different designs using a common, and often quite expensive, probe head 18.
Referring now to FIG. 2, an exemplary probe card 30 and integrated circuit 38 combination is shown in top view. The integrated circuit die 38 comprises internal circuitry that is connected to pads 42 that ring the periphery of the device. These pads 42 may comprise bonding pads. A bonding pad is a metal pad to which a metal wire is bonded, or welded, to create an interconnection between the device and an encapsulating package. The probe card 30 comprises a corresponding set of probe pins 34 that are aligned to physically touch each of the probe pads 42 in the DUT. The probe card 30 couples these probe pins 34 to interconnecting metal lines in the probe card structure that will connect to the probe head of the ATE system when the card 30 is installed in the probe head.
Referring now to FIG. 3, a cross section view of the probe card 30 and integrated circuit device 38 combination is shown. In the typical case, a plurality of circuit die 38 are formed on a single wafer. In this example, a single die 38 is contacted by the probe card 30 for testing. In practice, multiple dice could be probed at one time. The wafer is placed onto a wafer stage 50 and may be further held in place using vacuum. The probe card 30 is fixably attached to the probe head to provide electrical coupling to the ATE and to allow alignment and vertical movement. In a typical arrangement, the probe card 30 is aligned to the wafer under test at a first die location on the wafer. After successful alignment, the probe card 30 may then be indexed across the wafer to test each die 38. The probe card 30 is engaged for testing by vertically moving the card down until the probe pins 34 contact the probe pads 42.
Referring now to FIG. 4, an additional exemplary integrated circuit device 60 is shown. Pads 64 are again included around the periphery of the device 60. In this case, however, the integrated circuit device 60 is a flip chip device. In a flip chip device, raised bumps 68 are formed on the surface of the chip. Instead of wire bonding the die to a package, the circuit die 60 is flipped over and attached directly to a system-level circuit, such as a circuit board or a ceramic substrate. To facilitate this direct connection, the raised bumps commonly comprise a top layer of solder that can be easily melted to create a permanent connection to the circuit board. In the exemplary case, the solder bumps are connected to the wire bonding pads using a redistribution layer 72, such as metal lines.
Referring now to FIG. 5, another probe card is shown in cross section. This probe card is a vertical probe card comprising a probe head 80, probes 84, and a bottom guide plate 88. Vertical probe cards are commonly used for flip chip devices. Typically, vertical probe cards require 3 to 4 months to fabricate. More importantly, each integrated circuit design requires a customized card to fit the dimensions and pin out of the device. Further, due to the long fabrication time, the integrated circuit manufacturer must purchase several vertical probe cards for each device in case the probe card breaks. A significant goal of the present invention is to reduce the cost and lead time needed for probe cards.
Several prior art inventions relate to probe cards and to methods to test integrated circuits. U.S. Pat. No. 6,293,003 B1 to Sakurai et al shows an electronic part mounting device. U.S. Pat. No. 5,642,056 to Nakajima et al teaches a probe card apparatus having the ability to automatically correct the probe card posture prior to testing. U.S. Pat. No. 6,300,786 B1 to Doherty et al disclose a wafer test system having a probe card. The probe card contains an on-board multiplex circuit to allow testing of multiple dice in parallel.
A principal object of the present invention is to provide an effective and very manufacturable method to test multiple integrated circuit device designs using a single, probe card design.
A further object of the present invention is to provide a universal, probe card design to test a plurality of integrated circuit devices at the wafer level.
A yet further object of the present invention is to form integrated circuit probe pads in a fixed pitch array and to form probe card probe pins in the same fixed pitch array.
A yet further object of the present invention is to provide a method to test flip chip, integrated circuits using a universal probe card.
A yet further object of the present invention is to reduce probe card proliferation and cost.
A yet further object of the present invention is to provide a method to re-use a probe card as a design shrinks.
Another further object of the present invention is to provide a universal, probe card for testing multiple, integrated circuit device designs.
In accordance with the objects of this invention, a method to test multiple integrated circuit device designs using a single, probe card design is achieved. The method comprise providing a plurality of integrated circuit device designs each having a probe pad array comprising a fixed pitch. A first integrated circuit device having a first design is loaded on a probing stage. The first integrated circuit device is probed using a vertical probe card comprising a probe tip array. The probe tip array comprises the same fixed pitch. An automated tester is thereby coupled to the first integrated circuit device. The first integrated circuit device is tested with the automated tester. The steps of loading, probing, and testing are repeated on at least one other integrated circuit device having a differing design than the first integrated circuit device.
Also in accordance with the objects of this invention, a universal, probe card apparatus for testing multiple integrated circuit device designs on an automated tester is achieved. The probe card apparatus comprises an interconnection system. A probe tip array is coupled to the interconnection system such that a probed integrated circuit device is coupled to an automated tester. The probe tip array has a fixed pitch. The probe pad arrays on a plurality of integrated circuit device designs comprise the same fixed pitch.